Xor Gate

The PomeLabs XOR Gate Module (PML-XG-01) captures one of the most useful and counterintuitive operations in digital logic — output HIGH when inputs disagree, LOW when they match. It is the foundation of binary addition, parity checking, and controlled inversion. Built on the same configurable IC as the AND and NOT Gate Modules, it demonstrates how three entirely different logic behaviors emerge from the same silicon through configuration alone.

Revision: v1.0 | Part Number: PML-XG-01 | Series: PomeLabs Core Kit

Pinout

Xor Gate Pinout

Schematic

Xor Gate Schematic

Digital Twin

In the PomeLabs App, the PML-XG-01 is mirrored as a digital twin in both the Playground and inside any Connect Activity. Drive both inputs independently from the App and watch the XOR output update in real time — step through all four input combinations to build the truth table interactively.

Controls — parameters you can set from the App

Logic input A · pin S+_UL · toggle, HIGH / LOW

Drives the first XOR input. Output goes HIGH when this differs from input B.

Logic input B · pin S+_LL · toggle, HIGH / LOW

Drives the second XOR input. Output goes HIGH when this differs from input A.

UART TX — Upper-Left / Lower-Left · pins TX_UL-L, TX_LL-L · serial data source

Drives USART1/USART3 transmit lines through D1/D3 ESD protection.

UART TX — Upper-Right / Lower-Right · pins TX_UR-L, TX_LR-L · serial data source

Drives USART2/USART4 transmit lines through D2/D4 ESD protection.

Monitors — values streamed back from the module

Gate output Y · pins S+_UR / S+_LR · digital indicator, HIGH / LOW

Live XOR output. HIGH when inputs differ; LOW when identical. Updates in real time as inputs change.

UART RX — all four ports · serial data traces

Inbound data from downstream nodes through D1–D4 ESD protection back to the Backend MCU.

Datasheet

1. Overview

The PML-XG-01 implements a 2-input Exclusive-OR gate using the SN74LVC1G99DCUR (U1) — the same ultra-configurable gate used in the AND and NOT Gate Modules, here configured as a 3-state XOR. OE is permanently tied LOW.

Output Y is HIGH only when inputs A (S+_UL) and B (S+_LL) differ from each other. When both inputs are the same — both LOW or both HIGH — output Y is LOW. Y drives both S+_UR and S+_LR simultaneously. The XOR configuration is unique within the SN74LVC1G99 function table: input B is routed to configuration pin D rather than a dedicated input, making it the most instructive configuration to compare against AND and NOT when studying how programmable logic works.

Four USBLC6-2P6 ESD protection devices (D1–D4) protect all four UART ports.

2. BOM Components

Ref.	Type	Value / Part	Role on this module
U1	Configurable logic gate	SN74LVC1G99DCUR (TI)	Configured as 3-state XOR: C = L, D = Input 2 (B), OE = GND. Schmitt-trigger inputs ( $0.56\,\mathrm{V}$ hysteresis typ at $3.3\,\mathrm{V}$ ). SC-70-8 (DCUR) package.
D1	ESD protection IC	USBLC6-2P6 (ST)	IEC $61000-4-2$ Level $4$ ESD clamp on Upper-Left UART port. $3.5\,\mathrm{pF}$ max. SOT-666.
D2	ESD protection IC	USBLC6-2P6 (ST)	IEC $61000-4-2$ Level $4$ ESD clamp on Upper-Right UART port. Identical to D1.
D3	ESD protection IC	USBLC6-2P6 (ST)	IEC $61000-4-2$ Level $4$ ESD clamp on Lower-Left UART port. Identical to D1.
D4	ESD protection IC	USBLC6-2P6 (ST)	IEC $61000-4-2$ Level $4$ ESD clamp on Lower-Right UART port. Identical to D1.
R1, R2	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistors on UART TX/RX lines to $3.3\,\mathrm{V}$ .
p1–p4	Connector	Node headers	Four node connectors exposing $+5\,\mathrm{V}$ , GND, S+, S−, RX/TX, TX/RX to downstream modules.

3. Electrical Specifications

All values at $25\,\mathrm{{}^\circ C}$ unless otherwise noted. Gate specifications from TI SCES609G (SN74LVC1G99, Rev. G, Nov 2013). ESD protection from ST DS4260 Rev. 7 (USBLC6-2P6, Dec 2021).

3.1 U1 — SN74LVC1G99DCUR

3.1.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the device. Stress ratings only.

Parameter	Max Value	Unit
Supply voltage ( $V_{CC}$ )	$-0.5$ to $6.5$	V
Input voltage ( $V_I$ )	$-0.5$ to $6.5$	V
Output voltage — high-Z or power-off state ( $V_O$ )	$-0.5$ to $6.5$	V
Output voltage — high or low state ( $V_O$ )	$-0.5$ to $V_{CC} + 0.5$	V
Input clamp current ( $I_{IK}$ )	$-50$	mA
Output clamp current ( $I_{OK}$ )	$-50$	mA
Continuous output current ( $I_O$ )	$\pm 50$	mA
Continuous current through $V_{CC}$ or GND	$\pm 100$	mA
Thermal impedance $\theta_{JA}$ — DCU package	$227$	°C/W
Storage temperature ( $T_{stg}$ )	$-65$ to $+150$	°C

3.1.2 Recommended Operating Conditions

Parameter	Min	Max	Unit / Notes
Supply voltage ( $V_{CC}$ ) — operating	$1.65$	$5.5$	V
Input voltage ( $V_I$ )	$0$	$5.5$	V — inputs accept up to $5.5\,\mathrm{V}$ regardless of $V_{CC}$
Output voltage ( $V_O$ )	$0$	$V_{CC}$	V
High-level output current ( $I_{OH}$ ) @ $V_{CC} = 3.3\,\mathrm{V}$	—	$-24$	mA (sourcing)
Low-level output current ( $I_{OL}$ ) @ $V_{CC} = 3.3\,\mathrm{V}$	—	$24$	mA (sinking)
High-level output current ( $I_{OH}$ ) @ $V_{CC} = 5\,\mathrm{V}$	—	$-32$	mA (sourcing)
Low-level output current ( $I_{OL}$ ) @ $V_{CC} = 5\,\mathrm{V}$	—	$32$	mA (sinking)
Operating temperature ( $T_A$ )	$-40$	$125$	°C

4. Truth Table

OE	A (S+_UL)	B (S+_LL)	Y Output (S+_UR / S+_LR)
L	L	L	L — inputs identical (both LOW), output LOW
L	L	H	H — inputs differ, output HIGH
L	H	L	H — inputs differ, output HIGH
L	H	H	L — inputs identical (both HIGH), output LOW
H	X	X	Z — output disabled (high impedance)

6. Pin Descriptions

All signal pins are referenced to GND.

Pin / Net Name	Direction	Description
S+_UL	Input	Logic input A to U1. Upper-Left signal — first XOR input. Y HIGH when this differs from B.
S+_LL	Input	Logic input B to U1. Lower-Left signal — second XOR input. Y HIGH when this differs from A.
S+_UR / S+_LR	Output	XOR output Y. HIGH when inputs differ; LOW when identical. Drives both output channels simultaneously.
TX_UL-L / TX_LL-L	Input	UART transmit from Backend MCU (USART1/USART3). Through D1/D3 ESD protection.
RX_UL-L / RX_LL-L	Output	UART receive from Upper-Left and Lower-Left connectors. Through D1/D3 ESD protection.
TX_UR-L / TX_LR-L	Input	UART transmit from Backend MCU (USART2/USART4). Through D2/D4 ESD protection.
RX_UR-L / RX_LR-L	Output	UART receive from Upper-Right and Lower-Right connectors. Through D2/D4 ESD protection.
5V-Module	Power In	$5\,\mathrm{V}$ supply. Powers $V_{CC}$ of U1 and VBUS of D1–D4.
3V3	Power In	$3.3\,\mathrm{V}$ logic rail for pull-up resistors R1–R2 ( $4.7\,\mathrm{k\Omega}$ ).
GND	Ground	Common ground for all ICs and connectors.

7. Connection Guide & Common Errors

Correct power-up sequence:

Connect GND first, shared across all modules on the common bus.
Connect 5V-Module to a regulated $5\,\mathrm{V}$ source to power U1 and ESD clamp VBUS pins.
Connect 3V3 rail for UART pull-up resistors.
Verify OE is LOW (tied to GND on this module) — output should be active.
Apply logic signals to S+_UL and S+_LL and observe output on S+_UR / S+_LR.

Common wiring errors and consequences:

Mistake	Symptom	Correction
OE left floating on U1	Output enters high-Z randomly	Tie OE to GND. Never leave floating.
Input A or B left floating	Undefined input — XOR output unpredictable	Always drive both S+_UL (A) and S+_LL (B) from defined logic sources.
$V_{CC}$ to U1 exceeds $5.5\,\mathrm{V}$	U1 permanently damaged	Keep $V_{CC} \leq 5.5\,\mathrm{V}$ .
Input signal exceeds $5.5\,\mathrm{V}$	Clamp current flows; damage if $I_{IK} > 50\,\mathrm{mA}$	Add series resistor if overvoltage risk exists.
Output Y driving load $> 50\,\mathrm{mA}$	Current limit exceeded	Keep $I_O$ within $\pm 50\,\mathrm{mA}$ .
USBLC6-2P6 VBUS unconnected on D1–D4	ESD protection ineffective	Connect VBUS of D1–D4 to 5V-Module.
Confusing XOR with XNOR	Y LOW when inputs differ — opposite of expected	XOR: Y HIGH when inputs differ. XNOR: Y HIGH when inputs identical. Verify configuration pins.

Xor Gate

Pinout

Schematic

Digital Twin

Controls — parameters you can set from the App

Monitors — values streamed back from the module

Datasheet

1. Overview

2. BOM Components

3. Electrical Specifications

3.1 U1 — SN74LVC1G99DCUR

3.1.1 Absolute Maximum Ratings

3.1.2 Recommended Operating Conditions

4. Truth Table

6. Pin Descriptions

7. Connection Guide & Common Errors

Hands-on Labs

Xor Gate Onboarding

Half Adder

Parity Checker

Controlled Inverter

Use Cases

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