Not Gate

The PomeLabs NOT Gate Module (PML-NG-01) is the simplest possible logic operation made into a standalone educational building block. One input in, its complement out — every time, unconditionally. The same configurable IC powers the AND and XOR Gate Modules in this kit; here it is wired as a precision Schmitt-trigger inverter with $\pm 24\,\mathrm{mA}$ output drive and IEC 61000-4-2 Level 4 ESD protection on both UART ports.

Revision: v1.0 | Part Number: PML-NG-01 | Series: PomeLabs Core Kit

Pinout

Not Gate Pinout

Schematic

Not Gate Schematic

Digital Twin

In the PomeLabs App, the PML-NG-01 is mirrored as a digital twin in both the Playground and inside any Connect Activity. Toggle the input from the App and watch the output flip in real time — or drive the input from a signal generator module and observe the inversion on the App's live waveform view.

Controls — parameters you can set from the App

Logic input A · pin S+_L · toggle, HIGH / LOW

Drives the single inverter input. Set HIGH to get a LOW output; set LOW to get a HIGH output.

UART TX — Left / Right ports · pins TX_L-1, TX_L-2 · serial data source

Drives USART1/USART3 transmit lines through D1/D2 ESD protection to the Left and Right node connectors.

Monitors — values streamed back from the module

Inverter output Y · pin S+_R · digital indicator, HIGH / LOW

Live NOT gate output. Always the logical complement of input A when OE is LOW. Updates in real time as the input changes.

UART RX — Left / Right ports · pins RX_L-1, RX_L-2 · serial data traces

Inbound data from downstream nodes through D1/D2 ESD protection back to the Backend MCU.

Datasheet

1. Overview

The PML-NG-01 implements a logic inverter using the SN74LVC1G99DCUR (U1) — the same ultra-configurable single-gate device used in the AND Gate Module, here configured as a 3-state inverter (NOT gate). On this module, configuration pin D is hard-tied HIGH and pin C is hard-tied LOW on the PCB; OE is hard-tied LOW. Input pin A receives the user signal, and pin B is a "don't-care" per the TI Function Selection Table (the inverter row accepts B = H or L when this configuration is chosen).

When input A (S+_L) is HIGH, output Y (S+_R) is LOW. When A is LOW, Y is HIGH — the output is always the logical complement of the input. The Schmitt-trigger input stage ( $0.56\,\mathrm{V}$ hysteresis typ at $V_{CC}$ = $3\,\mathrm{V}$ ) cleanly handles slow or noisy signals without spurious output transitions. Two USBLC6-2P6 ESD protection devices (D1, D2) protect both UART communication ports.

Comparing the configuration of this module with the AND Gate Module reveals how a single IC delivers fundamentally different logic functions by changing only two pin tie-offs — a practical demonstration of programmable logic principles.

2. BOM Components

Ref.	Type	Value / Part	Role on this module
U1	Configurable logic gate	SN74LVC1G99DCUR (TI)	Configured as 3-state inverter: OE = GND, A = Input, B = don't care, C = GND, D = $V_{CC}$ . Schmitt-trigger input ( $0.56\,\mathrm{V}$ hysteresis typ at $V_{CC}$ = $3\,\mathrm{V}$ ). VSSOP-8 (DCU) package, $2.0 \times 3.1\,\mathrm{mm}$ .
D1	ESD protection IC	USBLC6-2P6 (ST)	IEC 61000-4-2 Level 4 ESD clamp on Left UART port. Rail-to-rail topology. $3.5\,\mathrm{pF}$ max I/O-to-GND. SOT-666 ( $1.6 \times 1.6\,\mathrm{mm}$ ).
D2	ESD protection IC	USBLC6-2P6 (ST)	IEC 61000-4-2 Level 4 ESD clamp on Right UART port. Identical to D1.
R1	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistor on Left-port UART line to 3V3. Holds the line at a defined HIGH idle state when no node is connected.
R2	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistor on Right-port UART line to 3V3. Identical role to R1.
p1, p2	Connector	Node headers	Left and Right node connectors exposing +5V, GND, S+, S−, RX/TX, TX/RX.

3. Electrical Specifications

All values at $25\,\mathrm{{}^\circ C}$ unless otherwise noted. Gate specifications from TI SCES609G (SN74LVC1G99, Rev. G, Nov 2013). ESD protection from ST DS4260 Rev. 7 (USBLC6-2P6, Dec 2021).

3.1 U1 — SN74LVC1G99DCUR

The SN74LVC1G99 features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is HIGH. When OE is LOW, the output state is determined by 16 patterns of the 4-bit input (A, B, C, D). Selectable functions include MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to $V_{CC}$ or GND.

3.1.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the device. Stress ratings only.

Parameter	Max Value	Unit
Supply voltage ( $V_{CC}$ )	$-0.5$ to $6.5$	V
Input voltage ( $V_I$ )	$-0.5$ to $6.5$	V
Output voltage — high-Z or power-off state ( $V_O$ )	$-0.5$ to $6.5$	V
Output voltage — high or low state ( $V_O$ )	$-0.5$ to $V_{CC} + 0.5$	V
Input clamp current ( $I_{IK}$ ), $V_I < 0$	$-50$	mA
Output clamp current ( $I_{OK}$ ), $V_O < 0$	$-50$	mA
Continuous output current ( $I_O$ )	$\pm 50$	mA
Continuous current through $V_{CC}$ or GND	$\pm 100$	mA
Package thermal impedance ( $\theta_{JA}$ ) — DCU package	$227$	°C/W
Storage temperature ( $T_{stg}$ )	$-65$ to $+150$	°C

3.1.2 Recommended Operating Conditions

Parameter	Min	Max	Unit / Notes
Supply voltage ( $V_{CC}$ ) — operating	$1.65$	$5.5$	V
Supply voltage ( $V_{CC}$ ) — data retention only	$1.5$	—	V
Input voltage ( $V_I$ )	$0$	$5.5$	V — input accepts up to $5.5\,\mathrm{V}$ regardless of $V_{CC}$
Output voltage ( $V_O$ )	$0$	$V_{CC}$	V
High-level output current ( $I_{OH}$ ) @ $V_{CC}$ = $3\,\mathrm{V}$	—	$-24$	mA — sourcing
Low-level output current ( $I_{OL}$ ) @ $V_{CC}$ = $3\,\mathrm{V}$	—	$24$	mA — sinking
High-level output current ( $I_{OH}$ ) @ $V_{CC}$ = $4.5\,\mathrm{V}$	—	$-32$	mA — sourcing
Low-level output current ( $I_{OL}$ ) @ $V_{CC}$ = $4.5\,\mathrm{V}$	—	$32$	mA — sinking
Input transition rise/fall rate ( $\Delta t / \Delta v$ ) @ $V_{CC}$ = $3.3\,\mathrm{V}$	—	$10$	ns/V
Operating temperature ( $T_A$ )	$-40$	$125$	°C

3.1.3 Electrical Characteristics

Parameter	Typical	Max	Condition
Positive-going input threshold ( $V_{T+}$ )	—	$1.97\,\mathrm{V}$	$V_{CC}$ = $3\,\mathrm{V}$ — Schmitt trigger
Negative-going input threshold ( $V_{T-}$ )	—	$1.24\,\mathrm{V}$	$V_{CC}$ = $3\,\mathrm{V}$
Input hysteresis ( $\Delta V_T = V_{T+} - V_{T-}$ )	$0.56\,\mathrm{V}$	$0.97\,\mathrm{V}$	$V_{CC}$ = $3\,\mathrm{V}$
Propagation delay ( $t_{pd}$ ) A → Y	—	$7.5\,\mathrm{ns}$	$V_{CC}$ = $3.3\,\mathrm{V}$ , $C_L$ = $15\,\mathrm{pF}$
Propagation delay ( $t_{pd}$ ) D → Y	—	$6.7\,\mathrm{ns}$	$V_{CC}$ = $3.3\,\mathrm{V}$ , $C_L$ = $15\,\mathrm{pF}$
Propagation delay ( $t_{pd}$ ) A → Y	—	$4.8\,\mathrm{ns}$	$V_{CC}$ = $5\,\mathrm{V}$ , $C_L$ = $15\,\mathrm{pF}$
Output enable time ( $t_{en}$ )	—	$5.8\,\mathrm{ns}$	$V_{CC}$ = $3.3\,\mathrm{V}$ , $C_L$ = $15\,\mathrm{pF}$
Output disable time ( $t_{dis}$ )	—	$7.0\,\mathrm{ns}$	$V_{CC}$ = $3.3\,\mathrm{V}$ , $C_L$ = $15\,\mathrm{pF}$
Quiescent supply current ( $I_{CC}$ )	—	$10\,\mathrm{\mu A}$	$V_I$ = $V_{CC}$ or GND, $I_O$ = $0$
Input capacitance ( $C_i$ )	$3.5\,\mathrm{pF}$	—	$V_{CC}$ = $3.3\,\mathrm{V}$
Output capacitance ( $C_o$ )	$6\,\mathrm{pF}$	—	$V_{CC}$ = $3.3\,\mathrm{V}$
Power dissipation capacitance ( $C_{pd}$ )	$22\,\mathrm{pF}$	—	$V_{CC}$ = $3.3\,\mathrm{V}$ , $f$ = $10\,\mathrm{MHz}$

4. Truth Table

On this module, OE = L, C = L, and D = H are hard-tied on the PCB — selecting the 3-state inverter function. Pin B is a don't-care for this configuration. The output is therefore the logical complement of input A:

OE	A (S+_L)	B	C	D	Y Output (S+_R)
L	L	X	L	H	H — input LOW → output HIGH (inverted)
L	H	X	L	H	L — input HIGH → output LOW (inverted)

The high-impedance state (Y = Z) is not reachable on this module because OE is hardwired LOW.

5. Logic Function Configuration Reference

The SN74LVC1G99 supports nine distinct logic functions selected by the static levels on A, B, C, D, and OE. The table below shows common configurations for reference — only the inverter configuration is wired on this PCB.

Function	OE	A	B	C	D
3-state inverter / NOT (this module)	L	Input	H or L	L	H
3-state buffer	L	Input	H or L	L	L
3-state 2-input AND	L	Input 1	Input 2	L	L
3-state 2-input NAND	L	Input 1	Input 2	H	L
3-state 2-input OR	L	Input 1	H	Input 2	L
3-state 2-input NOR	L	Input 1	H	Input 2	H
3-state 2-input XOR	L	Input 1	L	Input 2	H
3-state 2-input XNOR	L	H	L	Input 1	Input 2
Output disabled (high-Z)	H	X	X	X	X

6. Pin Descriptions

All signal pins are referenced to GND.

Pin / Net Name	Direction	Description
S+_L	Input	Logic input A to U1. Left channel — the single input to the inverter. When HIGH, Y goes LOW; when LOW, Y goes HIGH.
S+_R	Output	Inverter output Y. Logic complement of S+_L (OE is hardwired LOW).
TX_L/1	Input	UART transmit from Backend MCU to Left port. Routed through D1 ESD protection.
RX_L/1	Output	UART receive from Left connector back to Backend MCU. Through D1 ESD protection.
TX_R/2	Input	UART transmit from Backend MCU to Right port. Routed through D2 ESD protection.
RX_R/2	Output	UART receive from Right connector back to Backend MCU. Through D2 ESD protection.
5V-Module	Power In	$5\,\mathrm{V}$ supply. Powers $V_{CC}$ of U1 and the VBUS pin of D1/D2 (required for ESD clamp topology).
3V3	Power In	$3.3\,\mathrm{V}$ logic rail for pull-up resistors R1 and R2 ( $4.7\,\mathrm{k\Omega}$ each).
GND	Ground	Common ground for all ICs and connectors.

7. Connection Guide & Common Errors

Correct power-up sequence:

Connect GND first, shared across all modules on the common bus.
Connect 5V-Module to a regulated $5\,\mathrm{V}$ source. This powers $V_{CC}$ of U1 and the VBUS pins of the ESD ICs D1/D2.
Connect the 3V3 rail for the UART pull-up resistors R1 and R2.
Apply a logic signal to S+_L (input A). The inverted output appears immediately on S+_R — there is no enable step because OE is hardwired LOW on the PCB.

Logic-level reference (Schmitt-trigger input): at $V_{CC}$ = $3.3\,\mathrm{V}$ , the input must rise above $V_{T+} \approx 2.0\,\mathrm{V}$ to register as HIGH (driving Y LOW) and fall below $V_{T-} \approx 1.2\,\mathrm{V}$ to register as LOW (driving Y HIGH). Signals stuck inside the hysteresis band ( ${\approx}1.2\,\mathrm{V}$ – $2.0\,\mathrm{V}$ ) hold the previous logic state — useful for noise immunity, especially relevant when chaining multiple NOT gates into a ring oscillator where sub-threshold noise could otherwise propagate as glitches.

Common wiring errors and consequences:

Mistake	Symptom	Correction
Input S+_L left floating	Floating CMOS input drifts within the hysteresis band; output may oscillate randomly or hold an indeterminate state	Always drive S+_L from a defined logic source. Add a pull-down or pull-up resistor if the upstream signal source can disconnect.
$V_{CC}$ to U1 exceeds $5.5\,\mathrm{V}$	U1 permanently damaged (absolute max $6.5\,\mathrm{V}$ )	Keep 5V-Module rail $\leq 5.5\,\mathrm{V}$ .
Input signal on S+_L exceeds $5.5\,\mathrm{V}$	Input clamp current flows; permanent damage if $I_{IK}$ exceeds $50\,\mathrm{mA}$	Input is $5.5\,\mathrm{V}$ tolerant — never exceed it. Add a series resistor if your source can swing higher than $5.5\,\mathrm{V}$ .
Output Y driving load $> 50\,\mathrm{mA}$	Continuous output current absolute max exceeded — U1 may overheat or fail	Keep $I_O$ on S+_R within $\pm 50\,\mathrm{mA}$ absolute max. For sustained operation, design for $\pm 24\,\mathrm{mA}$ at $3\,\mathrm{V}$ or $\pm 32\,\mathrm{mA}$ at $4.5\,\mathrm{V}$ . Ring oscillator chains lightly load each stage and stay well within spec.
Very slow input edges (slower than $10\,\mathrm{ns/V}$ at $3.3\,\mathrm{V}$ )	Operation outside the guaranteed input transition rate; the Schmitt-trigger hysteresis improves robustness but TI does not specify behavior beyond this rate	Buffer slow analog-like signals with another logic stage if reliability is critical. The Schmitt input handles edges much slower than a plain CMOS input would, but is not unlimited.
USBLC6-2P6 VBUS pin on D1 or D2 unconnected	Rail-to-rail ESD topology cannot clamp positive surges — UART pins exposed to direct ESD strikes	Ensure 5V-Module is connected; it powers VBUS of both ESD ICs.
Powering input S+_L while 5V-Module is OFF	$I_{off}$ circuitry isolates U1 and prevents back-drive damage — designed-in safe condition, not a fault	No action needed; partial-power-down via $I_{off}$ is supported by the device.

Note: OE, C, and D are hard-tied to GND/ $V_{CC}$ on the PCB and are not user-accessible. The common floating-input mistakes that apply to bare SN74LVC1G99 designs (floating OE → high-Z output; floating C/D → undefined function) do not apply to this assembled module. Pin B is a don't-care for the inverter configuration and is also tied off on the PCB.