Node Voltage

The PomeLabs Node Voltage Module (PML-NV-01) is a multi-function power management and communication protection module — it controls, protects, and isolates in one board. Plug it in and instantly gain a current-limited power switch, a relay driver with built-in flyback protection, and ESD-hardened UART ports, all supervised by your Backend MCU.

Revision: v1.0 | Part Number: PML-NV-01 | Series: PomeLabs Core Kit

Pinout

Node Voltage Pinout

Schematic

Node Voltage Schematic

Digital Twin

In the PomeLabs App, the PML-NV-01 module is mirrored as a digital twin in both the Playground and inside any Connect Activity. The twin exposes the power switch, relay driver, and fault monitor as live controls — toggle them on screen and the change is pushed to the physical module over the Connect bus; fault events and rail states are streamed back in real time.

Controls — parameters you can set from the App

Power switch enable · pin GPOUT0 · toggle, HIGH / LOW

Drives the EN pin of U1 (TPS2069EDBVR). HIGH enables the 5V-Protected output rail; LOW disables it and discharges the output through the internal $500\,\mathrm{\Omega}$ resistor.

Relay control · pin GPOUT1 · toggle, HIGH / LOW

Drives the gate of U2 (SZNUD3124LT1G). HIGH energises relay coil K1; LOW releases it — the internal Zener clamp suppresses inductive kickback automatically.

Monitors — values streamed back from the module

Fault flag · pin GPIN0 · indicator, HIGH / LOW

Reflects the open-drain FLT output of U1 pulled up through R3 ( $4.7\,\mathrm{k\Omega}$ to 3V3). Goes LOW during overcurrent or overtemperature events; returns HIGH when the fault clears.

5V-Protected rail status · U1 · voltage readout

Confirms the switched output is live and within range. Useful for diagnosing UVLO or soft-start issues.

Relay state · K1 · indicator

Reflects whether the relay coil is energised based on GPOUT1 and U2 gate status.

Datasheet

1. Overview

The PML-NV-01 is organised into two functional layers. The FE Function block contains the active power-management circuitry: U1 (TPS2069EDBVR) is a current-limited, software-controlled USB-class power switch that converts a raw 5V-Module input into a protected 5V-Protected output rail under MCU supervision, while U2 (SZNUD3124LT1G) drives a relay coil (K1) directly from a logic-level GPIO with no external free-wheeling diode required. Outside the FE Function block, D1 and D2 (USBLC6-2P6) provide IEC 61000-4-2 Level 4 ESD protection on the two UART communication ports.

This architecture makes the PML-NV-01 the natural bridge between a Backend MCU and any load or node that requires controlled power, galvanic isolation, or hardened communication — without any external protection components.

Key characteristics at a glance:

U1 (TPS2069EDBVR): active-HIGH $1.5\,\mathrm{A}$ continuous-current power switch — built-in soft-start, $70\,\mathrm{m\Omega}$ $R_{DS(on)}$ at $5\,\mathrm{V}$ , output discharge ( $500\,\mathrm{\Omega}$ typ), reverse-current blocking, deglitched FLT flag ( $8\,\mathrm{ms}$ typ), and $2.13\,\mathrm{A}$ typical short-circuit current limit (±20% accuracy)
U2 (SZNUD3124LT1G): automotive-grade integrated low-side N-MOSFET relay driver — internal Zener clamp ( $34\,\mathrm{V}$ typ, $38\,\mathrm{V}$ max), no external free-wheeling diode required, AEC-Q101 qualified, drives relay coils up to $150\,\mathrm{mA}$ at $12\,\mathrm{V}$
K1 (G6K-2F-DC5): $5\,\mathrm{V}$ coil DPDT signal relay switched by U2, providing galvanic isolation for the load
FLT fault reporting from U1 to Backend MCU via GPIN0 (open-drain, pulled up through R3 $4.7\,\mathrm{k\Omega}$ to 3V3)
C3 ( $100\,\mathrm{nF}$ ) ceramic input bypass capacitor at U1 IN pin per TI application guidelines
Compatible with all modules in the PomeLabs Core Kit

2. BOM Components

Ref.	Type	Value / Part	Role on this module
U1	Power-distribution switch	TPS2069EDBVR (TI)	Primary power switch. N-channel MOSFET with active-HIGH enable. $1.5\,\mathrm{A}$ continuous output, $2.13\,\mathrm{A}$ typ short-circuit current limit (±20%). Provides built-in soft-start, output discharge ( $R_{DCHG}$ = $500\,\mathrm{\Omega}$ typ), reverse-current blocking, fast $1.5\,\mathrm{\mu s}$ typ overcurrent response, and $8\,\mathrm{ms}$ typ deglitched FLT reporting. SOT-23-5 (DBV) package, $2.9 \times 1.6\,\mathrm{mm}$ .
U2	Automotive inductive load driver	SZNUD3124LT1G (onsemi)	Integrated N-channel MOSFET relay driver with internal $10\,\mathrm{k\Omega}$ gate-to-drain and $100\,\mathrm{k\Omega}$ gate-to-source resistors plus internal Zener clamp ( $V_{BR(DSS)}$ = $28\,\mathrm{V}$ min, $34\,\mathrm{V}$ typ) — no external free-wheeling diode required. Logic-level gate input ( $V_{GS(th)}$ = $1.3$ – $2.0\,\mathrm{V}$ ). Drives relay coil K1 up to $150\,\mathrm{mA}$ continuous. AEC-Q101 qualified. SOT-23 (CASE 318) package. Note: marked as DISCONTINUED by onsemi (not recommended for new designs).
D1	ESD protection IC	USBLC6-2P6 (ST)	IEC 61000-4-2 Level 4 ESD clamp on UART Port 1 (TX_1 / RX_1). Rail-to-rail topology requires VBUS at $+5\,\mathrm{V}$ to clamp positive surges. $3.5\,\mathrm{pF}$ max I/O-to-GND. SOT-666 ( $1.6 \times 1.6\,\mathrm{mm}$ ).
D2	ESD protection IC	USBLC6-2P6 (ST)	IEC 61000-4-2 Level 4 ESD clamp on UART Port 2 (TX_2 / RX_2). Identical to D1.
K1	Relay	G6K-2F-DC5 (Omron)	$5\,\mathrm{V}$ DC coil signal relay switched by U2. Provides galvanic isolation between module logic and switched load. Coil energised when GPOUT1 is driven HIGH by Backend MCU.
C3	MLCC bypass capacitor	$100\,\mathrm{nF}$	Input bypass on 5V-Module rail at U1 IN pin. Required per TI TPS2069E application guidelines ( $\geq 100\,\mathrm{nF}$ ceramic close to IN/GND for local noise decoupling).
R1, R2	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistors on UART TX/RX lines to 3V3. Hold the lines at a defined HIGH idle state when no node is connected.
R3	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistor from FLT pin of U1 to 3V3. Required because FLT is open-drain — without this resistor the fault flag cannot present a HIGH idle level.

3. Electrical Specifications

All values at $25\,\mathrm{{}^\circ C}$ unless otherwise noted. Specifications from TI SLVSGZ7C (TPS20xxE, Rev. C, March 2025), onsemi NUD3124/D Rev. 15 (SZNUD3124LT1G, June 2024), and ST DS4260 Rev. 7 (USBLC6-2, December 2021).

3.1 U1 — TPS2069EDBVR

3.1.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the device. Stress ratings only.

Parameter	Value	Unit
Input voltage ( $V_{IN}$ )	$-0.3$ to $6$	V
Output voltage ( $V_{OUT}$ )	$-0.3$ to $6$	V
Enable voltage ( $V_{EN}$ )	$-0.3$ to $6$	V
FLT pin voltage ( $V_{FLT}$ )	$-0.3$ to $6$	V
Continuous output current ( $I_{OUT}$ )	Internally limited	—
ESD — Human Body Model (HBM)	$\pm 2000$	V
ESD — Charged Device Model (CDM)	$\pm 500$	V
ESD — IEC 61000-4-2 contact discharge, OUT pin	$\pm 8000$	V
ESD — IEC 61000-4-2 air-gap discharge, OUT pin	$\pm 15000$	V
Junction temperature ( $T_J$ )	$-40$ to $+125$	°C
Storage temperature ( $T_{stg}$ )	$-65$ to $+150$	°C

3.1.2 Recommended Operating Conditions

Parameter	Min	Nom	Max	Unit
Input voltage ( $V_{IN}$ )	$2.7$	$5$	$5.5$	V
Enable input voltage ( $V_{EN}$ )	$0$	—	$5.5$	V
Enable high-level input voltage ( $V_{IH}$ )	$1.8$	—	—	V
Enable low-level input voltage ( $V_{IL}$ )	—	—	$0.8$	V
Continuous output current ( $I_{OUT}$ )	—	—	$1.5$	A
FLT sink current ( $I_{FLT}$ )	$0$	—	$10$	mA
Junction temperature ( $T_J$ )	$-40$	—	$125$	°C
Ambient operating temperature ( $T_A$ )	$-40$	—	$85$	°C

3.1.3 Electrical Characteristics

Parameter	Min	Typ	Max	Condition
$R_{DS(on)}$ at $V_{IN}$ = $5\,\mathrm{V}$ or $3.3\,\mathrm{V}$	—	$70$	$105$	$\mathrm{m\Omega}$ — $I_O$ = $1.5\,\mathrm{A}$ , $T_J$ over full range
$R_{DS(on)}$ at $V_{IN}$ = $5\,\mathrm{V}$	—	$87$	—	$\mathrm{m\Omega}$ — $I_O$ = $1.5\,\mathrm{A}$ , $T_J$ = $85\,\mathrm{{}^\circ C}$
Output rise time ( $t_r$ )	—	$0.6$	$1.5$	$\mathrm{ms}$ — $V_{IN}$ = $5.5\,\mathrm{V}$ , $C_L$ = $1\,\mathrm{\mu F}$ , $R_L$ = $10\,\mathrm{\Omega}$
Output fall time ( $t_f$ )	—	$0.05$	$0.5$	$\mathrm{ms}$ — same conditions as $t_r$
Turn-on time ( $t_{ON}$ )	—	—	$3$	$\mathrm{ms}$ — $C_L$ = $100\,\mathrm{\mu F}$ , $R_L$ = $10\,\mathrm{\Omega}$
Turn-off time ( $t_{OFF}$ )	—	—	$3$	$\mathrm{ms}$ — same conditions as $t_{ON}$
Output discharge resistance ( $R_{DCHG}$ )	$400$	$500$	$810$	$\mathrm{\Omega}$ — $V_{IN}$ = $V_{OUT}$ = $5\,\mathrm{V}$ , disabled
Short-circuit current limit ( $I_{OS}$ ) at $25\,\mathrm{{}^\circ C}$	$1.71$	$2.13$	$2.55$	$\mathrm{A}$ — $V_{IN}$ = $5\,\mathrm{V}$ , OUT to GND
Short-circuit current limit ( $I_{OS}$ ) full temp range	$1.6$	$2.13$	$2.66$	$\mathrm{A}$ — $V_{IN}$ = $5\,\mathrm{V}$ , OUT to GND
Overcurrent response time ( $t_{IOS}$ )	—	$1.5$	—	$\mathrm{\mu s}$ — $V_{IN}$ = $5\,\mathrm{V}$ , $R_L$ = $50\,\mathrm{m\Omega}$
Supply current — disabled ( $I_{SD}$ ) at $25\,\mathrm{{}^\circ C}$	—	$0.5$	$1$	$\mathrm{\mu A}$ — $V_{EN}$ = $0\,\mathrm{V}$
Supply current — enabled ( $I_{SE}$ ) at $25\,\mathrm{{}^\circ C}$	—	$93$	$118$	$\mathrm{\mu A}$ — $V_{EN}$ = $5.5\,\mathrm{V}$ , $I_O$ = $0$
UVLO rising threshold	$2$	—	$2.6$	$\mathrm{V}$ — $V_{IN}$ rising
UVLO hysteresis	—	$75$	—	$\mathrm{mV}$ — at $25\,\mathrm{{}^\circ C}$
FLT output low voltage ( $V_{OL}$ )	—	—	$180$	$\mathrm{mV}$ — $I_{FLT}$ = $5\,\mathrm{mA}$
FLT off-state leakage	—	—	$1$	$\mathrm{\mu A}$ — $V_{FLT}$ = $5.5\,\mathrm{V}$
FLT deglitch time ( $T_{OC\_DEG}$ )	$6$	$8$	$12$	$\mathrm{ms}$ — assertion or de-assertion
Thermal shutdown rising threshold	$155$	$175$	$195$	°C
Thermal shutdown hysteresis	—	$10$	—	°C

3.2 U2 — SZNUD3124LT1G

3.2.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the device. Stress ratings only.

Parameter	Value	Unit
Drain-to-source voltage ( $V_{DSS}$ ) — continuous, $T_J$ = $125\,\mathrm{{}^\circ C}$	$28$	V
Gate-to-source voltage ( $V_{GSS}$ ) — continuous, $T_J$ = $125\,\mathrm{{}^\circ C}$	$12$	V
Drain current ( $I_D$ ) — continuous, $T_J$ = $125\,\mathrm{{}^\circ C}$	$150$	mA
Single-pulse drain-to-source avalanche energy ( $E_Z$ )	$250$	mJ
Peak power dissipation ( $P_{PK}$ ) — $1\,\mathrm{ms}$ square pulse	$20$	W
Inductive switching transient ( $E_{LD3}$ ) — drain-to-source	$300$	V
Reverse battery ( $10\,\mathrm{min}$ ), drain-to-source	$-14$	V
ESD — Human Body Model (HBM)	$2000$	V
Operating ambient temperature ( $T_A$ )	$-40$ to $+125$	°C
Junction temperature ( $T_J$ ) — max	$150$	°C
Storage temperature ( $T_{STG}$ )	$-65$ to $+150$	°C
Total power dissipation — SOT-23, $25\,\mathrm{{}^\circ C}$	$225$	mW
Thermal resistance junction-to-ambient ( $R_{\theta JA}$ ) — SOT-23	$556$	°C/W

3.2.2 Electrical Characteristics

Parameter	Min	Typ	Max	Condition
Drain-to-source sustaining voltage ( $V_{BR(DSS)}$ )	$28$	$34$	$38$	$\mathrm{V}$ — $I_D$ = $10\,\mathrm{mA}$
Drain-to-source leakage current ( $I_{DSS}$ )	—	—	$0.5$	$\mathrm{\mu A}$ — $V_{DS}$ = $12\,\mathrm{V}$ , $V_{GS}$ = $0\,\mathrm{V}$ , $25\,\mathrm{{}^\circ C}$
Gate-body leakage current ( $I_{GSS}$ )	—	—	$60$	$\mathrm{nA}$ — $V_{GS}$ = $3\,\mathrm{V}$ , $V_{DS}$ = $0\,\mathrm{V}$ , $25\,\mathrm{{}^\circ C}$
Gate threshold voltage ( $V_{GS(th)}$ )	$1.3$	$1.8$	$2.0$	$\mathrm{V}$ — $V_{GS}$ = $V_{DS}$ , $I_D$ = $1\,\mathrm{mA}$
Drain-to-source on-resistance ( $R_{DS(on)}$ )	—	$0.8$	—	$\mathrm{\Omega}$ — $I_D$ = $150\,\mathrm{mA}$ , $V_{GS}$ = $5\,\mathrm{V}$
Drain-to-source on-resistance ( $R_{DS(on)}$ )	—	$1.4$	—	$\mathrm{\Omega}$ — $I_D$ = $150\,\mathrm{mA}$ , $V_{GS}$ = $3\,\mathrm{V}$
Output continuous current ( $I_{DS(on)}$ )	$150$	$200$	—	$\mathrm{mA}$ — $V_{DS}$ = $0.25\,\mathrm{V}$ , $V_{GS}$ = $3\,\mathrm{V}$
High-to-low propagation delay ( $t_{PHL}$ )	—	$324$	—	$\mathrm{ns}$ — $V_{DS}$ = $12\,\mathrm{V}$ , $V_{GS}$ = $5\,\mathrm{V}$
Low-to-high propagation delay ( $t_{PLH}$ )	—	$1280$	—	$\mathrm{ns}$ — same conditions
Rise time ( $t_r$ )	—	$725$	—	$\mathrm{ns}$ — $V_{DS}$ = $12\,\mathrm{V}$ , $V_{GS}$ = $5\,\mathrm{V}$
Fall time ( $t_f$ )	—	$556$	—	$\mathrm{ns}$ — same conditions

4. Pin Descriptions

All signal pins are referenced to GND.

Pin / Net Name	Direction	Description
5V-Module	Power In	$5\,\mathrm{V}$ unregulated input supply. Feeds the IN pin of U1. Must be present and stable before EN is asserted. Also drives the K1 relay coil through the U2 low-side switch.
5V-Protected	Power Out	Switched, current-limited $5\,\mathrm{V}$ output from U1 OUT pin. Active only when GPOUT0 is HIGH. Protected against short circuits and overcurrent ( ${\approx}2.13\,\mathrm{A}$ typ limit, $1.5\,\mathrm{A}$ continuous rating). When U1 is disabled, the output is actively discharged through ${\approx}500\,\mathrm{\Omega}$ .
3V3	Power In	$3.3\,\mathrm{V}$ logic rail. Supplies the VBUS pin of D1/D2 (required for ESD clamp topology), the FLT pull-up R3, and the UART pull-ups R1/R2.
GPOUT0	Input	GPIO from Backend MCU. Drives the EN pin of U1. Pull HIGH ( $\geq 1.8\,\mathrm{V}$ ) to enable 5V-Protected; pull LOW ( $\leq 0.8\,\mathrm{V}$ ) to disable. Must not be left floating.
GPOUT1	Input	GPIO from Backend MCU. Drives the Gate of U2 through the internal $10\,\mathrm{k\Omega}$ resistor. Drive HIGH ( $\geq 2.0\,\mathrm{V}$ worst-case to fully turn on) to energise relay coil K1; drive LOW to release the relay.
GPIN0	Output (to MCU)	Open-drain FLT signal from U1, pulled up to 3V3 through R3 ( $4.7\,\mathrm{k\Omega}$ ). Active-LOW; asserted during overcurrent or thermal shutdown. The fault is deglitched by $8\,\mathrm{ms}$ typ on both edges.
TX_1-L / TX_2-L	Input	UART transmit from Backend MCU (USART1/USART2). Routed through D1/D2 ESD protection to the node-side connectors.
RX_1-L / RX_2-L	Output	UART receive from node connectors back to Backend MCU. Passed through D1/D2 ESD protection.
GND	Ground	Common ground reference shared across all ICs, the relay coil return path, and all connectors.

5. Connection Guide & Common Errors

Correct power-up sequence:

Connect GND first, ensuring it is shared across the Backend MCU, the PML-NV-01, and any downstream load on the common bus.
Connect 5V-Module to a regulated $5\,\mathrm{V}$ source. U1 remains in shutdown (output disabled, output actively discharged through ${\approx}500\,\mathrm{\Omega}$ ) until GPOUT0 is asserted HIGH.
Connect the 3V3 rail. This provides bias for the FLT pull-up R3, the UART pull-ups R1/R2, and the VBUS pin of the ESD ICs D1/D2.
After both supplies are stable, drive GPOUT0 HIGH to enable 5V-Protected. Soft-start ramps the output in ${\approx}0.6\,\mathrm{ms}$ typ ( $1.5\,\mathrm{ms}$ max at $V_{IN}$ = $5.5\,\mathrm{V}$ into $1\,\mathrm{\mu F}$ / $10\,\mathrm{\Omega}$ ).
Drive GPOUT1 HIGH only after the load side is ready. The relay K1 energises in roughly $1$ – $2\,\mathrm{ms}$ (typ propagation delay through U2 ${\approx}1.3\,\mathrm{\mu s}$ ; the rest is mechanical).
Read GPIN0 in firmware to detect FLT events. The signal is debounced internally — a transient overload shorter than $8\,\mathrm{ms}$ (typ) does not assert FLT, and a fault must persist $8\,\mathrm{ms}$ (typ) before GPIN0 goes LOW.

Note on FLT timing: the $8\,\mathrm{ms}$ ( $6$ – $12\,\mathrm{ms}$ ) deglitch window means software cannot rely on FLT to detect very short overcurrent events. Conversely, when clearing a fault by toggling EN, allow the deglitch period to elapse before re-arming the load.

Common wiring errors and consequences:

Mistake	Symptom	Correction
EN pin (GPOUT0) left floating	Output state is undefined per TI; charge-pump bias is unstable; 5V-Protected may glitch on or off	Always drive EN actively from GPOUT0. Tie to GND if the rail must be permanently OFF. EN must not be left open per the TI datasheet.
FLT pull-up R3 missing or rail floating	FLT line never goes HIGH (it is open-drain) — Backend MCU sees a permanent or floating fault and cannot distinguish good from faulted state	Connect R3 = $4.7\,\mathrm{k\Omega}$ from FLT to 3V3. 3V3 rail must be live for the pull-up to do its job.
Input bypass C3 too small or absent	Local noise/inrush at turn-on causes $V_{IN}$ to dip below the UVLO threshold ( ${\approx}2\,\mathrm{V}$ ) — U1 may UVLO-cycle on power-up; long input cables can also drive $V_{IN}$ above the $6\,\mathrm{V}$ absolute max via inductive overshoot	Place a $\geq 100\,\mathrm{nF}$ ceramic capacitor close to IN/GND per TI guideline. For long input cables or noisy supplies, add a $1$ – $22\,\mathrm{\mu F}$ ceramic (or a $10\,\mathrm{\mu F}$ on OUT) to absorb transients.
5V-Module exceeds $5.5\,\mathrm{V}$ (or $6\,\mathrm{V}$ abs max)	U1 permanently damaged	Keep 5V-Module within the $2.7\,\mathrm{V}$ – $5.5\,\mathrm{V}$ recommended operating range. Never exceed $6\,\mathrm{V}$ absolute max.
GPOUT1 high level too low for U2 gate	U2 MOSFET does not fully enhance — high $R_{DS(on)}$ , relay may not pull in cleanly, MOSFET dissipates excessive power	$V_{GS(th)}$ is $1.3\,\mathrm{V}$ min / $2.0\,\mathrm{V}$ max. Drive GPOUT1 $\geq 3\,\mathrm{V}$ to guarantee full enhancement; $5\,\mathrm{V}$ is ideal. The internal $10\,\mathrm{k\Omega}$ + $100\,\mathrm{k\Omega}$ network leaves the MOSFET OFF when GPOUT1 floats.
Free-wheeling diode added across K1 coil externally	Inductive kickback bypasses the U2 internal Zener clamp, slowing relay drop-out and partially defeating the integrated solution	U2's internal Zener clamp ( $V_{BR(DSS)}$ = $28\,\mathrm{V}$ min, $34\,\mathrm{V}$ typ) absorbs the kickback by design — no external free-wheeling diode is required or recommended.
Relay coil current exceeds $150\,\mathrm{mA}$	U2 $I_D$ rating exceeded; thermal stress on the SOT-23 ( $225\,\mathrm{mW}$ max dissipation)	Verify the K1 coil current at the operating supply voltage. The G6K-2F-DC5 has a coil resistance well above $80\,\mathrm{\Omega}$ , keeping $I_D$ well within spec.
5V-Module and 5V-Protected shorted together externally	Bypasses U1's short-circuit protection — the upstream supply sees the load directly with no current limit	Keep 5V-Module and 5V-Protected as separate nets. Only U1 bridges them.
USBLC6-2P6 VBUS pin unconnected on D1 or D2	Rail-to-rail ESD topology cannot clamp positive surges — UART RX pins exposed to direct ESD	Connect VBUS of both D1 and D2 to the 3V3 rail (or to 5V-Protected per the schematic). The rail must be powered before any cable is mated to a UART port.
Reading FLT immediately after enabling U1	False fault reported during the soft-start window	FLT is high-impedance during UVLO, and the $8\,\mathrm{ms}$ deglitch may not have settled. Wait at least $10\,\mathrm{ms}$ after asserting EN before sampling GPIN0.
Designing a new product around U2	SZNUD3124LT1G is marked "DISCONTINUED — not recommended for new design" by onsemi (NUD3124/D Rev. 15)	For new designs, contact onsemi for a recommended replacement (e.g. NCV8402 series or a discrete logic-level MOSFET + flyback diode). The PML-NV-01 retains the part for legacy compatibility only.